VLSI Implementation of Area-Error Optimized Compressor-Based Modified Wallace Tree Multiplier
- Title
- VLSI Implementation of Area-Error Optimized Compressor-Based Modified Wallace Tree Multiplier
- Description
- 2023 2nd International Conference on Trends in Electrical, Electronics and Computer Engineering, TEECCON 2023 pp.353-358
- Creator
- Balamanikandan A.; Suresh K.; Gnanaprakasam D.; Saranya K.
- Source
- <a href="https://www.scopus.com/inward/record.uri?eid=2-s2.0-85181536700&doi=10.1109%2fTEECCON59234.2023.10335812&partnerID=40&md5=1d03330fca94fec129239301d818bf1d" target="_blank" rel="noreferrer noopener">https://www.scopus.com/inward/record.uri?eid=2-s2.0-85181536700&doi=10.1109%2fTEECCON59234.2023.10335812&partnerID=40&md5=1d03330fca94fec129239301d818bf1d</a>
- Date
- 2023-01-01
Collection
Citation
Balamanikandan A.; Suresh K.; Gnanaprakasam D.; Saranya K., “VLSI Implementation of Area-Error Optimized Compressor-Based Modified Wallace Tree Multiplier,” CHRIST (Deemed To Be University) Institutional Repository, accessed February 8, 2025, https://archives.christuniversity.in/items/show/10122.