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    <name>Article</name>
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          <name>Title</name>
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              <text>An efficient adaptive reconfigurable routing protocol for optimized data packet distribution in network on chips</text>
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          <name>Subject</name>
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              <text>Dynamic XY routing algorithm; Network on chip; Random traffic profile; System on chip; Transpose traffic profile</text>
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              <text>The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable two-dimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.  2024 Institute of Advanced Engineering and Science. All rights reserved.</text>
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          <name>Creator</name>
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              <text>Sukumar P.G.; Krishnaiah M.; Velluri R.; Satish P.; Nagaraju S.; Puttaswamy N.G.; Srikantaswamy M.</text>
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              <text>International Journal of Electrical and Computer Engineering, Vol-14, No. 1, pp. 305-314.</text>
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              <text>Institute of Advanced Engineering and Science</text>
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              <text>2024-01-01</text>
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              <text>&lt;a href="https://doi.org/10.11591/ijece.v14i1.pp305-314" target="_blank" rel="noreferrer noopener"&gt;https://doi.org/10.11591/ijece.v14i1.pp305-314&lt;/a&gt;
&lt;br /&gt;&lt;br /&gt;&lt;a href="https://www.scopus.com/inward/record.uri?eid=2-s2.0-85183651138&amp;amp;doi=10.11591%2Fijece.v14i1.pp305-314&amp;amp;partnerID=40&amp;amp;md5=6a2df4965e88480bb8e309e96cce4627" target="_blank" rel="noreferrer noopener"&gt;https://www.scopus.com/inward/record.uri?eid=2-s2.0-85183651138&amp;amp;doi=10.11591%2fijece.v14i1.pp305-314&amp;amp;partnerID=40&amp;amp;md5=6a2df4965e88480bb8e309e96cce4627&lt;/a&gt;</text>
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          <name>Rights</name>
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              <text>All Open Access; Gold Open Access</text>
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              <text>ISSN: 20888708</text>
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              <text>Online</text>
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              <text>English</text>
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              <text>Sukumar P.G., Department of Computer Science and Engineering, JSS Academy of Technical Education, Bangalore, India; Krishnaiah M., Department of Electronics and Communications, Vidya Jyothi Institute of Technology, Hyderabad, India; Velluri R., Department of Computer Science and Engineering, CHRIST (Deemed to be University), Bangalore, India; Satish P., Department of Electronics and Communications, K.S. Institute of Technology, Bangalore, India; Nagaraju S., Department of Electrical and Electronics Engineering, Sri Jayachamarajendra College of Engineering, Mysore, India; Puttaswamy N.G., East Point College of Engineering and Technology, Bangalore, India; Srikantaswamy M., Department of Electronics and Communication Engineering, JSS Academy of Technical Education, Bangalore, India</text>
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