Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions
- Title
- Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions
- Creator
- Praghash K.; Arun Metha S.; Sai Tanuja B.; Preethi K.; Chandana N.P.N.S.
- Description
- Full adder is one of the important components in electronics, used for various fundamental processing algorithms such as addition and multiplication. The application of these full adders is included in but not limited to Very Large-Scale Integration (VLSI) and Digital Signal Processing (DSP). To provide scalability and reliability to the advanced algorithms for high-end applications, the designing system of full adder should be enhanced. So, in this paper, we intended to improve the efficiency of a full adder circuit to work under low power and delay conditions. The software we used in this project is MENTOR GRAPHICS using 180nm technology. The efficiency of the proposed transistor design is evaluated by analysing the power consumption, delay, PDP, capacitor load, delay w.r.t capacitance and PDP w.r.t capacitance. The parameters are compared between our proposed design and the literature schemes such as OLPFAD, DFEFA, DTLPCFA, and DPEHFA, respectively. It is evident that our proposed design outperforms the other. 2022, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.
- Source
- Wireless Personal Communications, Vol-126, No. 4, pp. 3041-3069.
- Date
- 2022-01-01
- Publisher
- Springer
- Subject
- Capacitance; Digital Signal Processing (DSP); Full adder; Power Delay Product (PDP); Transistor; Very Large-Scale Integration (VLSI)
- Coverage
- Praghash K., Department of Electronics and Communication Engineering, Christ University, Karnataka, Bengaluru, India; Arun Metha S., Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, AP, Vaddeswaram, India; Sai Tanuja B., Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, AP, Vaddeswaram, India; Preethi K., Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, AP, Vaddeswaram, India; Chandana N.P.N.S., Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, AP, Vaddeswaram, India
- Rights
- Restricted Access
- Relation
- ISSN: 9296212; CODEN: WPCOF
- Format
- Online
- Language
- English
- Type
- Article
Collection
Citation
Praghash K.; Arun Metha S.; Sai Tanuja B.; Preethi K.; Chandana N.P.N.S., “Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions,” CHRIST (Deemed To Be University) Institutional Repository, accessed February 26, 2025, https://archives.christuniversity.in/items/show/14866.