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    <name>Article</name>
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              <text>A reconfigurable integrated level shifted carrier based PWM method for modular multilevel converters</text>
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              <text>carrier based sinusoidal pulse width modulation; harmonic distortion; modular multilevel converters; pulse width modulation</text>
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              <text>This article presents a reconfigurable integrated level shifted carrier-based pulse width modulation (ILSC-PWM) method for modular multilevel converters (MMCs). The principles of basic level shifted carrier-based PWM (LSC-PWM) methods such as phase disposition PWM (PD-PWM), phase opposition disposition PWM (POD-PWM) and alternate phase opposition disposition PWM (APOD-PWM) methods are combined to develop the concept of reconfigurable ILSC-PWM method. The main objectives of the proposed reconfigurable ILSC-PWM method is to develop the pulse width modulated output voltage with both half-wave and quarter-wave symmetries and to reduce the total harmonic distortion (THD). A simplified mathematical approach is developed to formulate reconfigurable single ILSC wave for MMC with N number of submodules (SMs) per arm. The functionality and performance of the reconfigurable ILSC-PWM method are carried out on three-phase five-level MMC in MATLAB/Simulink. A hardware prototype of single-phase five-level MMC is designed for experimental validation. The proposed ILSC-PWM method is implemented on an Altera/Cyclone I series (EP1C12Q240C8N) field programmable gate array (FPGA). Computer Simulations and laboratory experimental results are presented.  2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.  2022 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.</text>
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              <text>Muthavarapu A.K.; Anjana K.G.; Biswas J.; Barai M.</text>
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              <text>IEEJ Transactions on Electrical and Electronic Engineering, Vol-17, No. 8, pp. 1148-1159.</text>
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              <text>John Wiley and Sons Inc</text>
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              <text>2022-01-01</text>
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              <text>&lt;a href="https://doi.org/10.1002/tee.23606" target="_blank" rel="noreferrer noopener"&gt;https://doi.org/10.1002/tee.23606&lt;/a&gt;
&lt;br /&gt;&lt;br /&gt;&lt;a href="https://www.scopus.com/inward/record.uri?eid=2-s2.0-85129043067&amp;amp;doi=10.1002%2Ftee.23606&amp;amp;partnerID=40&amp;amp;md5=827c0c17262df32f4e28c4a42c682fc4" target="_blank" rel="noreferrer noopener"&gt;https://www.scopus.com/inward/record.uri?eid=2-s2.0-85129043067&amp;amp;doi=10.1002%2ftee.23606&amp;amp;partnerID=40&amp;amp;md5=827c0c17262df32f4e28c4a42c682fc4&lt;/a&gt;</text>
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              <text>ISSN: 19314973</text>
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              <text>Muthavarapu A.K., Electrical and Electronics Engineering, Aditya Engineering College (A), Andhra Pradesh, Surampalem, 533437, India; Anjana K.G., Electrical Engineering, National Institute of Technology, Kerala, Calicut, 673601, India; Biswas J., Department of Computer Science, Christ University, Karnataka, Bengaluru, 560029, India; Barai M., Electrical Engineering, National Institute of Technology, Kerala, Calicut, 673601, India</text>
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