Hybrid architecture of digital filter for multi-standard transceivers

Title

Hybrid architecture of digital filter for multi-standard transceivers

Creator

Latha R.; Vanathi P.T.

Description

This paper addresses on three different architectures of digital decimation filter design of a multi-standard RF transceivers. Instead of using single stage decimation filter network, the filters are implemented in multiple stages using FPGA to optimize the area and power. The proposed decimation filter architectures reflect the considerable reduction in area & power consumption without degradation of performance. First, the types of decimation filter architectures are tested and implemented using conventional binary number system. Then the two different encoding schemes i. e. Canonic Signed Digit (CSD) and Minimum Signed Digit (MSD) are used for filter coefficients and then the architecture performances are tested using FPGA. The results of CSD and MSD based architectures show a considerable reduction in the area & power against the conventional number system based filter design implementation. The implementation results reflect that considerable reduction in area of 25. 64% and power reduction of 16. 45% are achieved using hybrid architecture. Research India Publications.

Source

International Journal of Applied Engineering Research, Vol-9, No. 21, pp. 11583-11600.

Date

2014-01-01

Publisher

Research India Publications

Subject

Digital filter; Digital signal processing; FPGA; Hardware reduction; Low power design; Multi-rate decimation filter

Coverage

Latha R., Department of Electronics and Communication Engineering, Christ University, Bangalore, 560 060, India; Vanathi P.T., Department of Electronics and Communication Engineering, P. S. G. College of Technology, Coimbatore, 641 004, India

Rights

Restricted Access

Relation

ISSN: 9734562

Format

Online

Language

English

Type

Article

Identifier

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84919756156&partnerID=40&md5=7e478f775a8bf432560d50ee719a7829