A Low Voltage and Low Power Analog Multiplier

Title

A Low Voltage and Low Power Analog Multiplier

Creator

Nayak A.G.; Bharath G.S.; Bhan I.; Mishra G.; Kumar V.

Description

In this research work, a low voltage analog multiplier has been realized through the utilization of a flipped voltage follower (FVF). The multiplier is characterized by its capacity to function at low power while exhibiting high gain. The exclusive use of transistors in its implementation renders it highly appropriate for fully integrated circuit applications. The multiplier has been developed using a supply voltage of 500 mV and an operating frequency of 25 KHz. The design consumes power of 8.23 uW. Moreover, a comparative study between the proposed multiplier and the conventional gilbert multiplier is presented in the paper. All simulations and layout designs have been conducted through the virtuoso analog design environment (ADE) of Cadence at 45 nm CMOS technology. 2023 IEEE.

Source

Proceedings of IEEE 2023 5th International Conference on Advances in Electronics, Computers and Communications, ICAECC 2023

Date

2023-01-01

Publisher

Institute of Electrical and Electronics Engineers Inc.

Subject

Analog Multipliers; flipped voltage follower; gilbert multiplier; low power; low voltage

Coverage

Nayak A.G., BMS College of Engineering, Department of ECE, Bangalore, India; Bharath G.S., BMS College of Engineering, Department of ECE, Bangalore, India; Bhan I., BMS College of Engineering, Department of ECE, Bangalore, India; Mishra G., BMS College of Engineering, Department of ECE, Bangalore, India; Kumar V., Christ University, Department of ECE, Bangalore, India

Rights

Restricted Access

Relation

ISBN: 979-835030544-9

Format

Online

Language

English

Type

Conference paper

Identifier

https://doi.org/10.1109/ICAECC59324.2023.10560170

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85198432650&doi=10.1109%2fICAECC59324.2023.10560170&partnerID=40&md5=4a1a14529b0603d20614703385efc992