Multiplier-free Realization of High throughout Transpose Form FIR Filter

Title

Multiplier-free Realization of High throughout Transpose Form FIR Filter

Creator

Sudharman S.; Bindiya T.S.

Description

This paper presents a multiplier-free realization of the block finite impulse response (FIR) filter in transpose form configuration using binary constant shifts method (BCSM). The proposed architecture is synthesized using Xilinx Vivado and Cadence RTL Encounter compiler for the area and power analysis and is compared with the existing works in the literature. The comparison highlights the advantages of the proposed architecture in terms of power, hardware complexity and throughput for realizing reconfigurable high throughput block FIR filters. 2020 IEEE.

Source

2020 12th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2020

Date

2020-01-01

Publisher

Institute of Electrical and Electronics Engineers Inc.

Subject

block filtering; common sub-expression elimination; Transpose structure

Coverage

Sudharman S., Christ (Deemed to Be University), Department of Electronics and Communication Engineering, Bangalore, Karnataka, India; Bindiya T.S., National Institute of Technology, Department of Electronics and Communication Engineering, Calicut, Kerala, India

Rights

Restricted Access

Relation

ISBN: 978-172816743-5

Format

Online

Language

English

Type

Conference paper

Identifier

https://doi.org/10.1109/CSNDSP49049.2020.9249595

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