FEC & BCH: Study and implementation on VHDL

Title

FEC & BCH: Study and implementation on VHDL

Creator

Chand E.; Ashok Reddy C.; Aswathakumara M.

Description

Channel encoding and Forward Error Correction is a crucial element of any communication system. This paper gives a brief overview of the fundamentals, mechanism and importance of Forward Error Correction. The design and implementation of a (63,36,5) BCH Codec is also projected in the later sections. All simulations are made on MATLAB R2018b and the VHDL implementations have been carried out using Xilinx Vivado 2018.2. 2019 IEEE

Source

Proceedings of the 3rd International Conference on Computing Methodologies and Communication, ICCMC 2019, pp. 952-957.

Date

2019-01-01

Publisher

Institute of Electrical and Electronics Engineers Inc.

Subject

BCH Codes; Channel Encoding; Forward Error Correction

Coverage

Chand E., Dept. of ECE, Faculty of Engineering, CHRIST (Deemed to be University), Bengaluru, India; Ashok Reddy C., FPGA Design, Eldaas Technologies Pvt. Ltd, Bengaluru, India; Aswathakumara M., Dept. of ECE, Faculty of Engineering, CHRIST (Deemed to be University), Bengaluru, India

Rights

Restricted Access

Relation

ISBN: 978-153867808-4

Format

Online

Language

English

Type

Conference paper

Identifier

https://doi.org/10.1109/ICCMC.2019.8819823

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