An ettective dynamic scheduler tor reconfigurable high speed computing system

Title

An ettective dynamic scheduler tor reconfigurable high speed computing system

Creator

Vucha M.; Rajawat A.

Description

High Speed Computing is a promising technology that meets ever increasing real-time computational demands through leveraging of flexibility and parallelism. This paper introduces a reconfigurable fabric named Reconfigurable High Speed Computing System (RHSCS) and offers high degree of flexibility and parallelism. RHSCS contains Field Programmable Gate Array (FPGA) as a Processing Element (PE). Thus, RHSCS made to share the FPGA resources among the tasks within single application. In this paper an efficient dynamic scheduler is proposed to get full advantage of hardware utilization and also to speed up the application execution. The addressed scheduler distributes the tasks of an application to the resources of RHSCS platform based on the cost function called Minimum Laxity First (MLF). Finally, comparative study has been made for designed scheduling technique with the existing techniques. The proposed platform RHSCS and scheduler with Minimum Laxity First (MLF) as cost function, enhances the speed of an application up to 80.30%. 2014 IEEE.

Source

Souvenir of the 2014 IEEE International Advance Computing Conference, IACC 2014, pp. 766-773.

Date

2014-01-01

Publisher

IEEE Computer Society

Subject

Field Programmable Gate Array; Minimum Laxity First; Reconfigurable High Speed Computing System; Reconfigurable Logic Unit

Coverage

Vucha M., MANIT, Bhopal, India, Christ University, Bangalore, India; Rajawat A., Dept. of ECE, MANIT, Bhopal, India

Rights

Restricted Access

Relation

0

Format

Online

Language

English

Type

Conference paper

Identifier

https://doi.org/10.1109/IAdCC.2014.6779420

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