Dublin Core The Dublin Core metadata element set is common to all Omeka records, including items, files, and collections. For more information see, http://dublincore.org/documents/dces/. Title A name given to the resource Faculty Publications Article Faculty Publications -Articles Dublin Core The Dublin Core metadata element set is common to all Omeka records, including items, files, and collections. For more information see, http://dublincore.org/documents/dces/. Creator An entity primarily responsible for making the resource Perumal, Vivek Karthick; Jayabalan, Ramesh; Paul, Eldho; Selvaraj, Dhanasekaran Title A name given to the resource VLSI Implementation of High-Speed and Area-Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications Date A point or period of time associated with an event in the lifecycle of the resource 01-01-2025 Source A related resource from which the described resource is derived Journal of Electrical and Computer Engineering;Volume;2025;Issue;1;Article No.;2638291; Identifier An unambiguous reference to the resource within a given context <a href="https://doi.org/10.1155/jece/2638291" target="_blank" rel="noreferrer noopener">https://doi.org/10.1155/jece/2638291</a> <br /><br /><a href="https://www.scopus.com/pages/publications/105019803776?origin=resultslist" target="_blank" rel="noreferrer noopener">https://www.scopus.com/pages/publications/105019803776?origin=resultslist</a> Coverage The spatial or temporal topic of the resource, the spatial applicability of the resource, or the jurisdiction under which the resource is relevant Perumal V.K., Department of Electronics and Communication Engineering, Sona College of Technology, Salem, India; Jayabalan R., Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, India; Paul E., Department of Electronics and Communication Engineering, School of Engineering and Technology, Christ University, Bangalore, India; Selvaraj D., Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, India Description An account of the resource This paper presents a VLSI implementation of a high-speed, area-efficient, multiplierless address generation architecture for the WiMAX deinterleaver, conforming to the IEEE 802.16e standard. The primary motivation of this work is to reduce hardware complexity and delay by eliminating multipliers, which are traditionally used in address generation. The proposed architecture is designed for FPGA and ASIC platforms, emphasizing simplicity, reduced latency, and efficient hardware utilization. The design supports standard modulation schemesQPSK, 16-QAM, and 64-QAMwith their respective code rates. Two key performance evaluations were conducted: Score 1, which refers to FPGA implementation on the Xilinx XC3S400, demonstrated a 13% increase in speed, and Score 2, based on ASIC analysis using 45-nm CMOS technology, and achieved improvements of 17% in power delay product (PDP) and 22% in area delay product (ADP) over existing architectures. These results confirm the architectures effectiveness for high-speed, low-power applications in modern communication systems. Copyright 2025 Vivek Karthick Perumal et al. Journal of Electrical and Computer Engineering published by John Wiley &amp; Sons Ltd. Subject The topic of the resource address generator; deinterleaver; FPGA; VLSI; WiMAX Publisher An entity responsible for making the resource available John Wiley and Sons Ltd Relation A related resource ISSN: 20900147; Language A language of the resource English Type The nature or genre of the resource Article Rights Information about rights held in and over the resource All Open Access; Gold Open Access; Green Open Access Format The file format, physical medium, or dimensions of the resource online