Dublin Core The Dublin Core metadata element set is common to all Omeka records, including items, files, and collections. For more information see, http://dublincore.org/documents/dces/. Title A name given to the resource Faculty Publications Conference Paper Faculty Publications- Conference Papers Dublin Core The Dublin Core metadata element set is common to all Omeka records, including items, files, and collections. For more information see, http://dublincore.org/documents/dces/. Creator An entity primarily responsible for making the resource Varshini, R. Loga; Ragesh, K.; Ramkumar, K.; Vel, R. Arun Shai Saravana; Kumar, R. Bharani Raj; Saravanan, M. Title A name given to the resource A Verilog-Based Design Framework for Real-Time Edge Detection in Image Processing Date A point or period of time associated with an event in the lifecycle of the resource 01-01-2025 Source A related resource from which the described resource is derived Proceedings of International Conference on Digital Innovations for Sustainable Solutions, ICDISS 2025; Identifier An unambiguous reference to the resource within a given context <a href="https://doi.org/10.1109/ICDISS68238.2025.11320708" target="_blank" rel="noreferrer noopener">https://doi.org/10.1109/ICDISS68238.2025.11320708</a> <br /><br /><a href="https://www.scopus.com/pages/publications/105033585274?origin=resultslist" target="_blank" rel="noreferrer noopener">https://www.scopus.com/pages/publications/105033585274?origin=resultslist</a> Coverage The spatial or temporal topic of the resource, the spatial applicability of the resource, or the jurisdiction under which the resource is relevant Varshini R.L., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Ragesh K., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Ramkumar K., School of Engineering and Technology, Christ (Deemed to be University), Bengaluru, India; Vel R.A.S.S., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Kumar R.B.R., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Saravanan M., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India Description An account of the resource This article details the design process of a real-time image processing system developed in Verilog. The design has proven highly effective in real-time image acquisition, buffering, and processing, with a focus on hardware and performance optimization. The principal modules are a line buffer for image frame storage, a convolution engine featuring edge detection filters such as Sobel and Prewitt, and a control unit responsible for data flow and synchronization. The architecture facilitates the transmission of image data from a camera, with processed images transmitted via VGA/HDMI interfaces. Focus is placed on attaining low latency, high throughput, and optimal utilization of FPGA platform resources. The technology is particularly relevant for autonomous systems, medical imaging, industrial automation, and surveillance, where real-time edge detection is crucial for decision-making. 2025 IEEE. Subject The topic of the resource Edge Detection; FPGA; Hardware Acceleration; Hardware Design; High-Throughput Architecture; Image Processing; Line Buffer; Low Latency; Parallel Processing; Real-Time Image Processing; Real-Time Processing; Verilog; VGA/HDMI Output Publisher An entity responsible for making the resource available Institute of Electrical and Electronics Engineers Inc. Relation A related resource ISBN: 979-833155641-9; Language A language of the resource English Type The nature or genre of the resource Conference paper Rights Information about rights held in and over the resource Restricted Access; Hardcopy may be available in the library Format The file format, physical medium, or dimensions of the resource online