Dublin Core The Dublin Core metadata element set is common to all Omeka records, including items, files, and collections. For more information see, http://dublincore.org/documents/dces/. Title A name given to the resource Faculty Publications Conference Paper Faculty Publications- Conference Papers Dublin Core The Dublin Core metadata element set is common to all Omeka records, including items, files, and collections. For more information see, http://dublincore.org/documents/dces/. Creator An entity primarily responsible for making the resource Gayathridevi, B.; Saravanan, M.; Ajayan, J.; Parthasarathy, Eswaran; Ramkumar, K.; Rahi, Shiromani Balmukund Title A name given to the resource Design and Implementation of a High-Speed Level Shifter at 45nm, 90nm, and 180nm Technology Nodes using Cadence Date A point or period of time associated with an event in the lifecycle of the resource 01-01-2025 Source A related resource from which the described resource is derived Proceedings of 7th International Conference on Inventive Material Science and Applications, ICIMA 2025;pp.138-143 Identifier An unambiguous reference to the resource within a given context <a href="https://doi.org/10.1109/ICIMA64861.2025.11073852" target="_blank" rel="noreferrer noopener">https://doi.org/10.1109/ICIMA64861.2025.11073852</a> <br /><br /><a href="https://www.scopus.com/pages/publications/105013848823?origin=resultslist" target="_blank" rel="noreferrer noopener">https://www.scopus.com/pages/publications/105013848823?origin=resultslist</a> Coverage The spatial or temporal topic of the resource, the spatial applicability of the resource, or the jurisdiction under which the resource is relevant Gayathridevi B., Sri Eshwar College of Engineering, Department of Ece, Tamilnadu, Coimbatore, India; Saravanan M., Sri Eshwar College of Engineering, Department of Ece, Tamilnadu, Coimbatore, India; Ajayan J., Sr University, Department of Ece, Telangana, Warangal, India; Parthasarathy E., Srm Institute of Science and Technology, Department of Ece, Kattankulathur, India; Ramkumar K., Christ University, School of Engineering and Technology, Department of Ece, Bangalore, India; Rahi S.B., University School of Information and Communication Technology, Gautam Buddha University Greater, Uttar Pradesh, India Description An account of the resource In this work, a CMOS inverter-based level shifter in Differential Cascode Voltage Switch Logic (DCVSL) is constructed and its operation is investigated. The width and length variations of transistors at three technological nodes 45, 90, and 180 nm are compared based on the circuit behaviour. A critical analysis of the impact of supply voltage scaling on NMOS and PMOS transistors is also presented. There is also a comparison of the effects of transistor widths and lengths, as well as supply voltage variations of 1.8V, 1.5V, and 1.0V, on circuit performance. Additionally, this study compares wavelength variation and its impact on device attributes. Dynamic power, static power, energy, and delay are evaluated at the transistor and direct current levels. The Cadence Virtuoso simulation tool illustrates the variations in inverter performance under various scaling conditions. The results demonstrate that careful optimization of transistor dimensions and supply voltage can significantly enhance the performance and power efficiency of the level shifter, providing valuable insights for low-power, high-speed VLSI applications. 2025 IEEE. Subject The topic of the resource CMOS; Differential Cascode Voltage Switch Logic; High speed transistor; Level shifter; NMOS; PMOS Publisher An entity responsible for making the resource available Institute of Electrical and Electronics Engineers Inc. Relation A related resource ISBN: 979-833152151-6; Language A language of the resource English Type The nature or genre of the resource Conference paper Rights Information about rights held in and over the resource Restricted Access; Hardcopy may be available in the library Format The file format, physical medium, or dimensions of the resource online