Design and Implementation of a High-Speed Level Shifter at 45nm, 90nm, and 180nm Technology Nodes using Cadence
subject: CMOS; Differential Cascode Voltage Switch Logic; High speed transistor; Level shifter; NMOS; PMOS
description: In this work, a CMOS inverter-based level shifter in Differential Cascode Voltage Switch Logic (DCVSL) is constructed and its operation is investigated. The width and length variations of transistors at three technological nodes 45, 90, and 180 nm are compared based on the circuit behaviour. A critical analysis of the impact of supply voltage scaling on NMOS and PMOS transistors is also presented. There is also a comparison of the effects of transistor widths and lengths, as well as supply voltage variations of 1.8V, 1.5V, and 1.0V, on circuit performance. Additionally, this study compares wavelength variation and its impact on device attributes. Dynamic power, static power, energy, and delay are evaluated at the transistor and direct current levels. The Cadence Virtuoso simulation tool illustrates the variations in inverter performance under various scaling conditions. The results demonstrate that careful optimization of transistor dimensions and supply voltage can significantly enhance the performance and power efficiency of the level shifter, providing valuable insights for low-power, high-speed VLSI applications. 2025 IEEE.
creator: Gayathridevi, B.; Saravanan, M.; Ajayan, J.; Parthasarathy, Eswaran; Ramkumar, K.; Rahi, Shiromani Balmukund
source: Proceedings of 7th International Conference on Inventive Material Science and Applications, ICIMA 2025;pp.138-143
publisher: Institute of Electrical and Electronics Engineers Inc.
date: 01-01-2025
rights: Restricted Access; Hardcopy may be available in the library
relation: ISBN: 979-833152151-6;
language: English
type: Conference paper
coverage: Gayathridevi B., Sri Eshwar College of Engineering, Department of Ece, Tamilnadu, Coimbatore, India; Saravanan M., Sri Eshwar College of Engineering, Department of Ece, Tamilnadu, Coimbatore, India; Ajayan J., Sr University, Department of Ece, Telangana, Warangal, India; Parthasarathy E., Srm Institute of Science and Technology, Department of Ece, Kattankulathur, India; Ramkumar K., Christ University, School of Engineering and Technology, Department of Ece, Bangalore, India; Rahi S.B., University School of Information and Communication Technology, Gautam Buddha University Greater, Uttar Pradesh, India