ItemArticle

VLSI Implementation of High-Speed and Area-Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications

Title
VLSI Implementation of High-Speed and Area-Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications
Creator
Perumal, Vivek Karthick; Jayabalan, Ramesh; Paul, Eldho; Selvaraj, Dhanasekaran
Description
This paper presents a VLSI implementation of a high-speed, area-efficient, multiplierless address generation architecture for the WiMAX deinterleaver, conforming to the IEEE 802.16e standard. The primary motivation of this work is to reduce hardware complexity and delay by eliminating multipliers, which are traditionally used in address generation. The proposed architecture is designed for FPGA and ASIC platforms, emphasizing simplicity, reduced latency, and efficient hardware utilization. The design supports standard modulation schemesQPSK, 16-QAM, and 64-QAMwith their respective code rates. Two key performance evaluations were conducted: Score 1, which refers to FPGA implementation on the Xilinx XC3S400, demonstrated a 13% increase in speed, and Score 2, based on ASIC analysis using 45-nm CMOS technology, and achieved improvements of 17% in power delay product (PDP) and 22% in area delay product (ADP) over existing architectures. These results confirm the architectures effectiveness for high-speed, low-power applications in modern communication systems. Copyright 2025 Vivek Karthick Perumal et al. Journal of Electrical and Computer Engineering published by John Wiley & Sons Ltd.
Source
Journal of Electrical and Computer Engineering;Volume;2025;Issue;1;Article No.;2638291;
Date
01-01-2025
Publisher
John Wiley and Sons Ltd
Subject
address generator; deinterleaver; FPGA; VLSI; WiMAX
Coverage
Perumal V.K., Department of Electronics and Communication Engineering, Sona College of Technology, Salem, India; Jayabalan R., Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore, India; Paul E., Department of Electronics and Communication Engineering, School of Engineering and Technology, Christ University, Bangalore, India; Selvaraj D., Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, India
Rights
All Open Access; Gold Open Access; Green Open Access
Relation
ISSN: 20900147;
Format
online
Language
English
Type
Article

Citation

Perumal, Vivek Karthick; Jayabalan, Ramesh; Paul, Eldho; Selvaraj, Dhanasekaran, “VLSI Implementation of High-Speed and Area-Efficient Multiplierless Address Generation Architecture for Deinterleaver in WiMAX Applications,” CHRIST (Deemed To Be University) Institutional Repository, accessed June 17, 2026, https://archives.christuniversity.in/items/show/23062.

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