ItemConference Paper

A Verilog-Based Design Framework for Real-Time Edge Detection in Image Processing

Title
A Verilog-Based Design Framework for Real-Time Edge Detection in Image Processing
Creator
Varshini, R. Loga; Ragesh, K.; Ramkumar, K.; Vel, R. Arun Shai Saravana; Kumar, R. Bharani Raj; Saravanan, M.
Description
This article details the design process of a real-time image processing system developed in Verilog. The design has proven highly effective in real-time image acquisition, buffering, and processing, with a focus on hardware and performance optimization. The principal modules are a line buffer for image frame storage, a convolution engine featuring edge detection filters such as Sobel and Prewitt, and a control unit responsible for data flow and synchronization. The architecture facilitates the transmission of image data from a camera, with processed images transmitted via VGA/HDMI interfaces. Focus is placed on attaining low latency, high throughput, and optimal utilization of FPGA platform resources. The technology is particularly relevant for autonomous systems, medical imaging, industrial automation, and surveillance, where real-time edge detection is crucial for decision-making. 2025 IEEE.
Source
Proceedings of International Conference on Digital Innovations for Sustainable Solutions, ICDISS 2025;
Date
01-01-2025
Publisher
Institute of Electrical and Electronics Engineers Inc.
Subject
Edge Detection; FPGA; Hardware Acceleration; Hardware Design; High-Throughput Architecture; Image Processing; Line Buffer; Low Latency; Parallel Processing; Real-Time Image Processing; Real-Time Processing; Verilog; VGA/HDMI Output
Coverage
Varshini R.L., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Ragesh K., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Ramkumar K., School of Engineering and Technology, Christ (Deemed to be University), Bengaluru, India; Vel R.A.S.S., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Kumar R.B.R., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India; Saravanan M., Department of ECE, Sri Eshwar College of Engineering, Tamilnadu, Coimbatore, India
Rights
Restricted Access; Hardcopy may be available in the library
Relation
ISBN: 979-833155641-9;
Format
online
Language
English
Type
Conference paper

Citation

Varshini, R. Loga; Ragesh, K.; Ramkumar, K.; Vel, R. Arun Shai Saravana; Kumar, R. Bharani Raj; Saravanan, M., “A Verilog-Based Design Framework for Real-Time Edge Detection in Image Processing,” CHRIST (Deemed To Be University) Institutional Repository, accessed June 19, 2026, https://archives.christuniversity.in/items/show/25964.

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